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M68AW127B
1Mbit (128K x8), 3.0V Asynchronous SRAM
FEATURES SUMMARY s SUPPLY VOLTAGE: 2.7 to 3.6V
s s s s s s
Figure 1. Packages
128K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
SO32 (MC)
TSOP32 8 x 20 mm (N)
TSOP32 8 x 13.4 mm (NK)
August 2003
1/20
M68AW127B
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 12. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . 15 TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline. . . . . . . . . . . . . . . . . . . . . . . . 16 TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data . . . . . . . . . . . . . . . . 16 TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . 17 TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data . . . . . . . . . . . . . . 17 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M68AW127B
SUMMARY DESCRIPTION The M68AW127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply.
This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW127B is available in SO32, TSOP32 8x20mm and TSOP32 8x13.4mm packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A16 Address Inputs Data Input/Output Chip Enable Chip Enable Output Enable Write Enable Supply Voltage Ground
VCC
DQ0-DQ7 E1
17 A0-A16
8 DQ0-DQ7
E2 G W
W E1 E2 G M68AW127B
VCC VSS
VSS
AI05972b
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M68AW127B
Figure 3. SO Connections Figure 4. TSOP Connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1
32
8 9
M68AW127B
25 24
16
17
AI05931b
VCC A15 E2 W A13 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
A11 A9 A8 A13 W E2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1
32
8 9
M68AW127B
25 24
16
17
AI05973c
G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
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M68AW127B
Figure 5. Block Diagram
A16 ROW DECODER A7 MEMORY ARRAY
DQ7
I/O CIRCUITS COLUMN DECODER
DQ0 E1 E2 A0 A6 Ex
W
G
AI05471
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol IO
(1)
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Parameter Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Power Dissipation
Value 20 -55 to 125 -65 to 150 -0.3 to 4.6 -0.5 to VCC +0.5 1
Unit mA C C V V W
TA TSTG VCC VIO (2) PD
Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 3.6V only.
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M68AW127B
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages -40 to 85C 100pF 3.0k 3.1k 1ns/V 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC M68AW127B 2.7 to 3.6V 0 to 70C
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST CL Output Transition Timing Reference Voltage VCC R2 0.7VCC 0.3VCC
AI04831
OUT
0V
CL includes JIG capacitance
AI05814
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M68AW127B
Table 4. Capacitance
Symbol CIN COUT Parameter (1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1MHz, VCC = 3.0V.
Table 5. DC Characteristics
Symbol ICC1 (1,2) Parameter Supply Current Test Condition VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA VCC = 3.6V, f = 1MHz, IOUT = 0mA VCC = 3.6V, f = 1MHz, IOUT = 0mA 0V VIN VCC 0V VOUT VCC VCC = 3.6V, E1 VCC - 0.2V, E2 0.2V, f = 0 70 100 2.2 70 VIL Input Low Voltage 100 Output High Voltage Output Low Voltage IOH = -1mA 70 100 VOL
Note: 1. 2. 3. 4.
Min 70 100 70
Typ 6.0 25
Max 15 35 2
Unit mA mA mA mA mA A A A A V V V V V
Operating Supply Current ICC2 (3) Operating Supply Current (READ) Operating Supply Current (WRITE) ILI ILO (4) ISB VIH Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage
1.5 100 10 -1 -1 2.5 0.3
5 15 1 1 15 10 VCC + 0.3 0.8 0.6
-0.3 -0.3 2.4 2.2
VOH
IOL = 2.1mA
0.4
V
Average AC current, cycling at tAVAV minimum. E1 = VIL, E2 = VIH, VIN = VIH or VIL. E1 0.2V or E2 VCC -0.2V, VIN 0.2V or VIN VCC -0.2V. Output disabled.
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M68AW127B
OPERATION The M68AW127B has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High), or Chip Select is asserted (E2 = Low). An Output Enable (G) signal provides a high-speed, tri-state Table 6. Operating Modes
Operation Read Read Write Deselect Deselect
Note: X = VIH or VIL.
control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E1 as summarized in the Operating Modes table (Table 6).
E1 VIL VIL VIL VIH X
E2 VIH VIH VIH X VIL
W VIH VIH VIL X X
G VIH VIL X X X
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z Hi-Z
Power Active (ICC) Active (ICC) Active (ICC) Standby (ISB) Standby (ISB)
Read Mode The M68AW127B is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, Chip Enable (E1) is asserted and Chip Select (E2) is de-asserted. This provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins
within tAVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV.
Figure 8. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI05474
Note: E1 = Low, E2 = High, G = Low, W = High.
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M68AW127B
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV A0-A16 tAVQV tELQV E1 VALID tAXQX tEHQZ
E2
tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI05476
tGHQZ
Note: Write Enable (W) = High.
Figure 10. Chip Enable Controlled, Standby Mode AC Waveforms
E1
E2 ICC ISB tPU 50%
AI05477
tPD
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M68AW127B
Table 7. Read and Standby Mode AC Characteristics
M68AW127B Symbol tAVAV tAVQV tAXQX (1) tEHQZ (2,3) tELQV tELQX (1) tGHQZ (2,3) tGLQV tGLQX (2) tPD (4) tPU (4) Read Cycle Time Address Valid to Output Valid Data hold from address change Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable or UB/LB High to Power Down Chip Enable or UB/LB Low to Power Up Parameter 70 Min Max Min Max Max Min Max Max Min Max Min 70 70 5 25 70 5 25 35 5 0 70 100 100 100 15 30 100 10 30 50 5 0 100 ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters.
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M68AW127B
Write Mode The M68AW127B is in the Write mode whenever the W and E1 pins are Low and the E2 pin is High. Either the Chip Enable input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of E1 being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH, respectively, and is determined by the latter occurring edge.
The Write cycle can be terminated by the earlier rising edge of E1, or W. If the Output is enabled (E1 = Low, E2 = High and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1, whichever occurs first, and remain valid for tWHDX or tEHDX.
Figure 11. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E1 tELWH tWHAX
E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI05478
tWHQX
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M68AW127B
Figure 12. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E1 tELEH tEHAX
E2 tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05479
tWLEH
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M68AW127B
Table 8. Write Mode AC Characteristics
M68AW127B Symbol tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX (1) tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 70 60 0 60 0 30 30 0 0 60 60 0 0 5 60 20 60 100 100 80 0 80 0 40 40 0 0 80 80 0 0 5 70 30 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AW127B
Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V (1) tCDR E1 VDR - 0.2V E1 tR
AI05980
Note: 1. For 100ns speed class VDR 2.0V.
Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 2.7V
VDR > 1.5V (1) tCDR E2 E2 0.2V
AI05957B
tR
Note: 1. For 100ns speed class VDR 2.0V.
Table 9. Low VCC Data Retention Characteristics
Symbol ICCDR (1) Parameter Supply Current (Data Retention) Test Condition VCC = 1.5V, E1 VCC -0.2V or E2 0.2V, f = 0 70 100 0 70 100 E1 VCC -0.2V or E2 0.2V, f = 0 70 100 tAVAV 5 1.5 2.0 Min Typ Max 4.5 5 Unit A A ns ns ms V V
Chip Deselected to Data tCDR (1,2) Retention Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention)
Note: 1. All other Inputs at VIH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V.
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M68AW127B
PACKAGE MECHANICAL Figure 15. SO32 - 32 lead Plastic Small Outline, Package Outline
D
16 1
E
E1
17
32
A2 B SO-C e A1 CP
A C L1 L
Note: Drawing is not to scale.
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b c D E E1 e L L1 CP 1.270 0.102 2.565 0.356 0.152 20.142 11.176 13.868 - 0.584 1.194 2.819 0.508 0.305 20.752 11.430 14.376 - 0.991 1.600 0.10 0.050 Min Max 2.997 0.004 0.101 0.014 0.006 0.793 0.440 0.546 - 0.023 0.047 0.111 0.020 0.012 0.817 0.450 0.566 - 0.039 0.063 0.004 Typ Min Max 0.118 inches
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M68AW127B
Figure 16. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: Drawing is not to scale.
Table 11. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 E e L N 0.500 19.800 18.300 7.900 - 0.500 0 32 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.250 0.210 0.100 20.200 18.500 8.100 - 0.700 5 0.0197 0.7795 0.7205 0.3110 - 0.0197 0 32 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0098 0.0083 0.0039 0.7953 0.7283 0.3189 - 0.0276 5 inches
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M68AW127B
Figure 17. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: Drawing is not to scale.
Table 12. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C D D1 E e L N CP 32 0.10 13.40 11.80 8.00 0.50 0.22 0.10 - - - - 0.40 0 0.21 - - - - 0.60 5 32 0.0039 0.5276 0.4646 0.3150 0.0197 0.05 0.91 Min Max 1.20 0.15 1.05 0.0087 0.0039 - - - - 0.0157 0 0.0083 - - - - 0.0236 5 0.0020 0.0358 Typ Min Max 0.0472 0.0059 0.0413 inches
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M68AW127B
PART NUMBERING Table 13. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 127 = 1Mbit (128K x8) Option 1 B = 2 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 70 = 70ns 10 = 100ns Package MC = SO32 N = TSOP32 (8 x 20 mm) NK = TSOP32 (8 x 13.4 mm) Operative Temperature 1 = 0 to 70C 6 = -40 to 85 C Shipping T = Tape & Reel Packing M68AW127 B L 70 N 6 T
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68AW127B
REVISION HISTORY Table 14. Document Revision History
Date January 2002 Version 1.0 First Issue DC Characteristics table clarified (Table 5) E1 Controlled, Low VCC Data Retention AC Waveforms clarified (Figure 13) Low VCC Data Retention Characteristics table clarified (Table 9) Ordering Information Scheme clarified (Table 13) 70ns speed class added SO32 and TSOP32 8x13.4mm package options added Commercial code clarified Title and header layout modified. Commercial code modified. Label corrected on "E2 Controlled, Low VCC Data Retention AC Waveforms" figure TSOP Package connections modified (Figure 5) Revision Details
09-May-2002
2.0
01-Jul-2002 11-Sep-2002 02-Oct-2002 09-Oct-2002 16-Apr-2003 21-Aug-2003
3.0 4.0 4.1 4.2 4.3 4.4
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M68AW127B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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